(a) Field of the Invention
The present invention relates to a drive circuit detecting a slow signal transition. More specifically it relates to a drive circuit which quickly detects a slow change of a signal on a signal line having a large resistance and a large capacitance to reduce the delay of the signal transition in various circuits such as a multistage pass transistor circuit, a word line drive circuit of a memory, a clock circuit, and a bus circuit.
(b) Description of the Related Art
FIG. 1A shows a conventional high-speed drive circuit adapted for quickly detecting a signal which rises or falls slowly.
The high-speed drive circuit includes serial pMOS transistors 102 and 103 each having a gate connected to an input signal line 101, serial nMOS transistors 105 and 106 connected in series to the pMOS transistors 102 and 103 and 106 each having a gate connected to input signal line 101, a delay circuit 108 having an input connected to an input signal line 101 to output an inverted and delayed signal of an input signal, and a pMOS transistor 104 connected in parallel to transistor 102 and an nMOS transistor 107 connected in parallel to transistor 106, each of which has a gate connected to the output of the delay circuit 108. Transistors 102 through 107 as combined constitute an inverter 109 for supplying an output signal through output signal line 110. Transistors 104 and 107 have a large channel width as compared to transistors 102 and 106, respectively. The delay circuit 108 is formed by, for example, an odd number of cascaded inverters.
Operation of the high-speed drive circuit of FIG. 1A will be described with reference to FIG. 1B. In an initial steady state, the input signal is at a low level, so that transistors 102, 103 and 107 are on and transistors 104, 105 and 106 are off. Hence, the output signal line 110 is at a high level. In a transient state, while the level of an input signal supplied through input signal line 101 rises, the delay circuit 108 maintains, for a predetermined period of time, its original output level which is the inverse of the level of the original input signal. When the input signal exceeds the threshold of the transistors, transistors 102 and 103 turn off and transistors 105 and 106 turn on while transistors 104 and 107 remain in their initial states. Hence, the output signal line 110 is driven to a low level by transistor 107 additionally to transistors 105 and 106 at a high speed.
Similarly, the inverter 109 operates at a high speed when the input signal falls from high to low. In short, the inverter 109 has a low logical threshold voltage when the input signal rises while has a high logical threshold voltage when the input falls.
As a result, if the high speed drive circuit as described above is used to detect a signal transmitted through a signal line having a high parasitic resistance and capacitance in which the level of a signal slowly changes, the signal transition is quickly detected to reduce or recover the delay of the signal transmission.
In the conventional high-speed drive circuit of FIG. 1A, since the delay circuit is formed by a plurality of cascaded inverters to have an inherent delay time, it cannot be used if the period of tile input signal is longer than the inherent delay time. Namely, the drive circuit cannot be operated at frequencies lower than a frequency determined by the delay time.
Moreover, since the level of the output signal immediately changes after the level of the input signal starts to change, the drive circuit suffers from a small noise margin.
FIG. 2A shows a different example of a conventional drive circuit having a large noise margin.
The drive circuit shown in FIG. 2A has an inverter 121 including pMOS transistors 112, 113 and 114 and nMOS transistors 115, 116 and 117 and having a similar configuration to that of inverter 109 of FIG. 1A, and an inverter 118 which receives the output signal 120 of inverter 121. Each of pMOS transistor 114 and nMOS transistor 117 of the inverter 121 has a large channel width and a gate connected to tile output of the inverter 118.
As shown in FIG. 2B, when an input signal supplied to the drive circuit of FIG. 2A changes its level, the threshold of inverter 121 varies to prevent the change of the level of the output signal 120. Hence, the level of the output signal at output signal line 119 changes after the level of the input signal sufficiently changes. Hence, the logical threshold voltage of the drive circuit is high when the level of the input signal rises while low when the level of the input signal falls.
As a result, the drive circuit of FIG. 2A is used in an input/output buffer subjected to a large noise to increase the noise margin of the circuit.
In the conventional drive circuit having a large noise margin as described above, the level of the output signal does not change until the level of the input signal sufficiently changes. Therefore, if the above drive circuit is used to drive a signal line having a high parasitic resistance and capacitance, propagation delay of signal increases.
Accordingly, a drive circuit is desired which has a large noise margin and operates in a wide frequency range, at a high speed even for a slow signal transition of an input signal.